gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: january 2001 document no. 521 - 96 - 05 data sheet gs9032 features ? smpte 259m and 540mb/s compliant serializes 8-bit or 10-bit data autostandard, adjustment free operation minimal external components (no loop filter components required) isolated, quad output, adjustable cable driver power saving secondary cable driver disable 3.3v and 5.0v cmos/ttl compatible inputs lock detect indication smpte scramble and nrzi coding bypass option edh support with gs9001, gs9021 or edh fpga code application smpte 259m and 540mb/s parallel to serial interfaces for video cameras, vtrs, and signal generators; generic parallel to serial conversion. description the gs9032 encodes and serializes smpte 125m and 244m bit parallel digital video signals, and other 8-bit or 10-bit parallel formats. this device performs sync detection, parallel to serial conversion, data scrambling (using the x 9 + x 4 + 1 algorithm), 10x parallel clock multiplication and conversion of nrz to nrzi serial data. the gs9032 features auto standard and adjustment free operation for data rates to 540mb/s with a single vco resistor. other features include a lock detect output, nrzi encoding, smpte scrambler bypass, a sync detect disable, and an isolated quad output cable driver suitable for driving 75 ? loads. the complementary cable driving output swings can be adjusted independently or the secondary differential cable driver can be powered down. the gs9032 requires a single +5 volt or -5 volt supply and typically consumes 675mw of power while driving four 75 ? loads. block diagram ordering information part number package temperature gs9032 - cvm 44 pin tqfp 0c to 70c gs9032 - ctm 44 pin tqfp tape 0c to 70c auto/manual select (auto/man) lock detect (lock det) sdo1 enable serial digital outputs parallel clock input (pclkin) p load s clk s clk /10 loop bandwidth control (lbwc) r vco+ r vco- data rate select ss[2:0] mute reset reset sync detect disable (sync dis) bypass bypass parallel to serial converter & nrz to nrzi data in (pd0-pd9) 10 3 10 8 input latch 2 10 sync detect smpte scrambler pll sdo0 sdo0 sdo1 sdo1 genlinx ? ii gs9032 digital video serializer
gennum corporation 521 - 96 - 05 2 gs9032 absolute maximum ratings parameter value supply voltage (v s = v cc -v ee )5.5v input voltage range (any input) v ee gennum corporation 521 - 96 - 05 3 gs9032 ac electrical characteristics v cc = 5v, v ee = 0v, t a =0 c to 70 c unless otherwise specified. parameter symbol conditions min typ max units notes test level serial data bit rate br sdo r vco = 374 ? 143 - 540 mb/s smpte 259m 1 serial data outputs signal swing v sdo r load = 37.5 ? , r set = 54.9 ? 740 800 860 mvp-p 1 min. swing (adjusted) v sdomin r load = 37.5 ? , r set = 73.2 ? - 600 - mvp-p 7 max. swing (adjusted) v sdomax r load = 37.5 ? , r set = 43.2 ? -1000-mvp-p 1 sd rise/fall times t r , t f 20% - 80% 400 - 700 ps 7 sd overshoot/undershoot - - 7 % 1 7 output return loss o rl at 540mhz 15 - - db 1 7 lock time t lock worst case - - 5 ms 6 min. loop bandwidth bw min 270mb/s lbwc = grounded : bw min - 220 - khz 7 typical loop bandwidth bw typ 270mb/s lbwc = floating : bw min - 500 - khz 7 max. loop bandwidth bw max 270mb/s lbwc = v cc : 10 bw min -1.7-mhz 7 intrinsic jitter (6 ) 143mb/s lbwc = floating - 0.07 - ui 1 177mb/s lbwc = v cc -0.07- 270mb/s - 0.08 - 360mb/s - 0.09 - 540mb/s - 0.11 - data & clock inputs (pd[9:0] pclkin) t su setup time at 25 c2.5--ns 1 t h hold time at 25 c2.0--ns 1 test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1,2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/characterization data of similar product. notes 1. depends on pcb layout. 10
gennum corporation 521 - 96 - 05 4 gs9032 pin connections gs9032 top view 44 43 42 41 40 39 38 37 36 35 34 r vco+ lf+ v ee r vco- lf- v cc1 lbwc nc sync dis v ee v ee1 33 32 31 30 29 28 27 26 25 24 23 auto/man bypass r set1 v ee sdo1 sdo1 v ee sdo0 sdo0 v ee pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pclkin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 v cc2 v ee 2 c osc r set0 ss1 ss2 sdo1 enable lock det v ee3 sso v cc3 reset pin descriptions number symbol type description 1-10 pd9 - pd0 i cmos or ttl compatible parallel data inputs. pd0 is the lsb and pd9 is the msb. 11 pclkin i cmos or ttl compatible parallel clock input. 12 v ee3 - most negative power supply connection for parallel data and clock inputs. 13 v cc3 - most positive power supply connection for parallel data and clock inputs. 14 c osc i master timer capacitor. a capacitor should be added to decrease the system clock frequency when an external capacitor is used across lf+ and lf- (nc if not used). 15, 16, 21 ss2, ss1, ss0 i data rate selection when in manual mode. these pins are not used in auto mode. 17 v cc2 - most positive power supply connection for internal logic and digital circuits. 18 v ee2 - most negative power supply connection for internal logic and digital circuits. 19 sdo1 enable i enable pin for the secondary cable driver (sdo1 and sdo1 ). connect to most negative power supply to enable. leave open to disable (do not connect to v cc ). 20 lock det o ttl level which is high when the internal pll is locked. 22 r set0 i external resistor used to set the data output amplitude for sdo0 and sdo0 . 23, 26, 29 v ee - most negative power supply connection for shielding (not connected). 24, 25 sdo0 , sdo0 o primary, current mode, 75 ? cable driving output (inverse and true) 27, 28 sdo1 , sdo1 o secondary, current mode, 75 ? cable driving output (inverse and true) 30 r set1 i external resistor used to set the data output amplitude for sdo1 and sdo1 .
gennum corporation 521 - 96 - 05 5 gs9032 typical performance curves (v s = 5v, t a = 25 c unless otherwise shown. guard band tested to 70 c only.) fig. 1 rise/fall times vs. temperature fig. 2 supply current vs. temperature (sdo0 & sdo1 on) 31 bypass i when high, the smpte scrambler and nrz encoder are bypassed. 32 auto/man i autostandard or manual mode selectable operation. 33 reset i resets the scrambler when asserted. 34 v cc1 - most positive power supply connection for analog circuits. 35 v ee1 - most negative power supply connection for analog circuits. 36, 38 r vco +, r vco - i differential vco current setting resistor that sets the vco frequency. 37 nc i no connect. 39, 43 v ee - most negative power supply connection (substrate). 40 lbwc i ttl level loop bandwidth control that adjusts the pll bandwidth to optimize for lowest jitter. if the pin is set to ground the loop bandwidth is bw min . if the pin is left floating, the loop bandwidth is approximately 3 bw min , if the pin is tied to v cc the loop bandwidth is approximately10 bw min 41, 42 lf+, lf- i differential loop filter pins to optimize loop transfer performance at low loop bandwidths (nc if not used). 44 sync dis i sync detect disable. logic high disables sync detection. logic low allows 8 bit operation by mapping 000-003 to 000 and 3fc-3ff to 3ff. pin descriptions number symbol type description 5.25 fall 4.75 rise 5.0 rise 5.0 fall 5.25 rise 4.75 fall 020406080 500 490 480 470 460 450 440 430 420 rise / fall time (ps) temperature (?c) 4.75 5.0 5.25 020406080 155 150 145 140 135 130 125 current (ma) temperature ( ? c)
gennum corporation 521 - 96 - 05 6 gs9032 fig. 3a output swing vs. temperature (1000mv) fig. 3b output swing vs. temperature (800mv) fig. 4 waveforms fig. 5 timing diagram fig. 6a loop filter voltage vs. temperature (360 mode) fig. 6b loop filter voltage vs. temperature (540 mode) 4.75 5.0 5.25 020406080 1.01 1.005 1.000 0.995 0.99 output swing (v) temperature ( ? c) 4.75 5.0 5.25 020406080 0.8075 0.805 0.8025 0.800 0.7975 0.795 0.7925 output swing (v) temperature ( ? c) t su t hold t clkl = t clkh parallel clock plck 50% parallel data pdn e a v s a v 4? sc data stream active video & h blanking t r s active video t r s t r s active video & h blanking 4:2:2 data stream e a v s a v h blnk h blnk sync detect sync detect sync detect xxx 3ff 000 000 xxx xxx 3ff 000 000 xxx pclk in pdn 020406080 160 140 120 100 80 60 40 20 0 lf+ lf- (mv) temperature ( ? c) 020406080 40 20 0 -20 -40 -60 lf+ lf- (mv) temperature ( ? c)
gennum corporation 521 - 96 - 05 7 gs9032 fig. 7 loop bandwidth vs. data rate fig. 8 output jitter vs. lbwc fig. 9 output jitter vs. data rate (optimum lbw setting) fig. 10 output eye diagram (270mb/s) fig. 11 output eye diagram (540mb/s) lbwc to v cc lbwc floating lbwc grounded 0 143 177 270 360 540 3500 3000 2500 2000 1500 1000 500 0 loop bandwidth (khz) data rate (mb/s) grounded floating v cc 600 500 400 300 200 100 0 jitter p-p (ps) loop bandwidth control (lbwc) for a data rate of 270mb/s 0 100 200 300 400 500 600 500 400 300 200 100 0 jitter p-p (ps) data rate (mb/s)
gennum corporation 521 - 96 - 05 8 gs9032 detailed description the gs9032 serializer is a bipolar integrated circuit used to convert parallel data into a serial format according to the smpte 259m standard. the device encodes both eight and ten bit ttl-compatible parallel signals producing serial data rates up to 540mb/s. it operates from a single five volt supply and is packaged in a 44 pin tqfp. functional blocks within the device include the input latches, sync detector, parallel to serial converter, smpte scrambler, nrz to nrzi converter, internal cable driver, pll for 10x parallel clock multiplication and lock detect. the parallel data (pd0-pd9) and parallel clock (pclkin) are applied via pins 1 through 11 respectively. 1. sync detector the sync detector makes the system compatible with eight or ten bit data. it looks for the reserved words 000-003 and 3fc-3ff in ten bit hexadecimal, or 00 and ff in eight bit hexadecimal, used in the trs-id sync word. when the occurrence of either all zeros or all ones at inputs pd2-pd9 is detected, the lower two bits pd0 and pd1 are forced to zeros or ones respectively. for non-smpte standard parallel data, the sync detector can be disabled through a logic input, sync detect disable (44). 2. scrambler the scrambler is a linear feedback shift register used to pseudo-randomize the incoming serial data according to the fixed polynomial (x 9 +x 4 +1). this minimizes the dc component in the output serial data stream. the nrz to nrzi converter uses another polynomial (x+1) to convert a long sequence of ones to a series of transitions, minimizing polarity effects. these functions can be disabled by setting the bypass pin (31) high. 3. phase locked loop the pll performs parallel clock multiplication and provides the timing signal for the serializer. it is composed of a phase/frequency detector (with no dead zone), charge pump, vco , a divide-by-ten counter, and a divide-by-two counter. the phase/frequency detector allows a wider capture range and faster lock time than with a phase discriminator alone. the discrimination of frequency eliminates harmonic locking. with this type of discriminator, the pll can be over- damped for good stability without sacrificing lock time. the charge pump delivers a 'charge packet' to the loop filter which is proportional to the system phase error. internal voltage clamps are used to constrain the loop filter voltage between approximately 1.8 and 3.4 volts. the vco is a differential low phase noise, factory trimmed design that provides increased immunity to pbc noise and precise control of the vco centre frequency. the vco can operate in excess of 800mhz and has a pull range of 15% about the centre frequency. the single external resistor, r vco , sets the vco frequency (see figure 12) . 4. vco centre frequency selection for a given r vco value, the vco can oscillate at one of two frequencies. when ss0=logic 1, the vco centre frequency corresponds to the l curve. for ss0=logic 0, the vco centre frequency corresponds to the h curve ( h is approximately 1.5 x l ). fig. 12 the recommended r vco value for auto rate smpte 259m applications is 374 ? ( see the typical application circuit ). this value prevents false standards indication in auto mode. for non-smpte applications (where data rates are x2 harmonically related) use figure 12 to determine the r vco values. the vco and an internal divider generate the pll clock. divider moduli of 1, 2, and 4 allow the pll to lock to data rates from 143mb/s to 540mb/s. the divider modulus is set by the auto/man , and ss[2:0] pins ( see truth table for further details ). in addition, a manually selectable modulus 8 divider allows operation at data rates as low as 18mb/s when r vco is increased to 1k ? . when the loop is not locked, the lock detect circuit mutes the serial data outputs. when the loop is locked, the lock detect output is available from pin 20 and is high. the true and complement serial data, sdo and sdo , are available from pins 24, 25, 27 and 28. these outputs drive four 75 ? co-axial cables with smpte level serial digital video signals. to disable the outputs from pins 27 and 28 (sdo1 , sdo1), remove the resistor connected to the r set1 pin (30) and float the sdo1 enable pin (19). note: do not connect pin 19 to v cc . r set calculation: where r load = r pull-up || z 0 100 200 300 400 500 600 700 800 0 200 400 600 800 1000 1200 1400 1600 1800 vco frequency (mhz) r vco ( ? ) h l sso=1 sso=0 r set 1.154 r load v sdo -------------------------------------- - =
gennum corporation 521 - 96 - 05 9 gs9032 typical application circuit (smpte auto mode) truth table (manual mode) data rate (mb/s) ss2 ss1 ss0 divider moduli vco frequency 143 0 0 0 4 h 177 0 0 1 2 l 270 0 1 0 2 h 360 0 1 1 1 l 540 1 0 0 1 h 451018 l 681108 h 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 gs9032 v ee3 v cc3 nc (c osc ) ss2 ss1 v cc2 v ee2 sdo1_en lock ss0 r set0 sync_dis v ee lf- lf+ lbwc v ee r vco nc r vco+ v ee1 v cc1 reset auto/man bypass_en r set1 v ee sdo1 sdo1 v ee sdo0 sdo0 v ee pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pclkin v cc j2 j1 j3 j4 v cc v cc v cc ss0* ss1* ss2* v cc v cc 374 100n 54.9 75 75 l r l r l r l r 1 1 1 1 75 75 100n 54.9 220 j1 lbwc 100n 100n 10k 0 * see truth table for settings. nc in auto mode. parallel clock input parallel data inputs l = 8.2nh r = 75 ? lock 100n all resistors on ohms, all capacitors in farads, unless otherwise stated. 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 v cc reset v cc
521 - 96 - 05 10 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation c-101, miyamae village, 2-10-42 miyamae, suginami-ku tokyo 168-0081, japan tel. +81 (03) 3334-7700 fax. +81 (03) 3247-8839 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that th ey are free from patent infringement. ? copyright may 1998 gennum corporation. all rights reserved. printed in canada. gs9032 package dimensions 10.00 12.00 10.00 0.80 0.30 12.00 0.20 max radius 0.08 min. radius 0.60 0.15 0.20 min 12 ? typ 12 ? typ 1.00 0.10 1.10 0.127 7 ? max 0 ? min 0 min pin 1 0.20 min all dimensions in millimetres 44 pin tqfp revision notes: updated the electrical characteristics tables. for latest product information, visit www.gennum.com. caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation document identification data sheet the product is in production. gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
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